Realistic Delay Modeling in Satisfiability - Based Timing Analysis

Circuit delay computation taking into account the existence of false paths represents a significant and computationally complex problem. Existing research work has focused mainly on path sensitization models and algorithms, and on gate and interconnect delay models. Nevertheless, work in these two main areas has evolved separately, and so most path sensitization models and algorithms assume very rudimentary gate and interconnect delay models. In this paper we propose a modeling framework for circuit delay computation as a sequence of instances of prop-ositional satisfiability. This framework is used to capture several path sensitization models under the unit delay model. Moreover, several algorithms for propositional satisfiability are evaluated seeking to illustrate the computational challenges posed by the circuit delay computation problem. Finally, realistic delay models taking into account extracted interconnect delays and fanout data are incorporated into the proposed circuit delay computation framework in order to experimentally evaluate its applicability .